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MX25L1602
16M-BIT [16M x 1] CMOS SERIAL FLASH EEPROM
FEATURES
GENERAL * 16,777,216 x 1 bit structure * 256 Equal Sectors with 8K-byte each - Any sector can be erased * 4096 Equal Segments with 512-byte each - Provides sequential output within any segment * Single Power Supply Operation - 3.0 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1V to Vcc +1V * Low Vcc write inhibit is equal to or less than 2.5V PERFORMANCE SOFTWARE FEATURES * Input Data Format
- 1-byte Command code, 3-byte address, 1-byte byte
address * 512-byte Sequential Read Operation * Built in 9-bit (A0 to A8) pre-settable address counter to support the 512-byte sequential read operation * Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algroithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) * Status Register Feature - Provides detection of program and erase operation completion. - Provides auto erase/ program error report HARDWARE FEATURES * SCLK Input - Serial clock input * SI Input - Serial Data Input * SO Output - Serial Data Output * PACKAGE - 28-pin SOP (330mil)
* High Performance - Fast access time: 20MHz serial clock (50pF + 1TTL
Load) - Fast program time: 5ms/page (typical, 128-byte per page) - Fast erase time: 300ms/sector (typical, 8K-byte per sector) Low Power Consumption - Low active read current: 10mA (typical) at 17MHz - Low active programming current: 10mA (typical) - Low active erase current: 10mA (typical) - Low standby current: 30uA (typical, CMOS) Minimum 100,000 erase/program cycle
*
*
P/N: PM0819
REV. 1.0, MAR. 04, 2003
1
MX25L1602
GENERAL DESCRIPTION
The MX25L1602 is a CMOS 16,777,216 bit serial Flash EEPROM, which is configured as 2,097,152 x 8 internally. The MX25L1602 features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS input. The MX25L1602 provide sequential read operation on whole chip. The sequential read operation is executed on a segment (512 byte) basis. User may start to read from any byte of the segment. While the end of the segment is reached, the device will wrap around to the beginning of the segment and continuously outputs data until CS goes high. After program/erase command is issued, auto program/ erase algorithms which program/erase and verify the specified page locations will be executed. Program command is executed on a page (128 bytes) basis, and erase command is executed on both chip and sector (8K bytes) basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion and error flag status of a program or erase operation. When the device is not in operation and CS is high, it is put in standby mode and draws less than 30uA DC current. The MX25L1602 utilizes MXIC's proprietary memory cell which reliably stores memory contents even after 100,000 program and erase cycles.
PIN CONFIGURATIONS
28-PIN SOP (330 mil)
NC TEST DU NC NC NC NC NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC GND VCC NC NC NC SI SO CS SCLK NC NC NC NC
PIN DESCRIPTION
SYMBOL CS TEST(1) SI SO SCLK VCC GND DU(2) NC DESCRIPTION Chip Select Test Mode Select Serial Data Input Serial Data Output Clock Input + 3.3V Power Supply Ground Do Not Use(for Test Mode only) No Internal Connection
MX25L1602
Note: 1.TEST input is used for in-house testing and must be tied to ground during normal user operation. 2.DU pin is used for in-house testing and can be tied to VCC, GND or open for normal operation.
P/N: PM0819
2
REV. 1.0, MAR. 04, 2003
MX25L1602
BLOCK DIAGRAM
Address Generator
X-Decoder
Memory Array (4096 x 4096)
Page Buffer Data Register Y-Decoder
SI
CS
Mode Logic
State Machine
Sense Amplifier HV Generator
Output Buffer
SO SCLK Clock Generator
P/N: PM0819
3
REV. 1.0, MAR. 04, 2003
MX25L1602
COMMAND DEFINITION
Command (byte) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th Action 52H AD1 AD2 AD3 BA X X X X n bytes read out until CS goes high Output status byte until CS goes high Clear status byte Output vendor code until CS goes high Start to erase at CS rising edge Start to erase at CS rising edge Load n bytes data to buffer until CS goes high & start to program 83H X 89H 85H X F1H AD1 AD2 F4H X X F2H AD1 AD2 AD3 BA Read Array Status Read Clear Status Read ID Sector Erase Chip Erase Page Program
Note: 1.X is dummy cycle and is necessary 2.AD1 to AD3 are address input data 3.BA is byte address
1-byte command code Bit7(MSB) Bit6 3-byte address(0 to 0FFFH) AD1: X X AD2: A16 A15 AD3: X X 1-byte byte address(0 to 7FH) BA: X A6 Note: A20 to A13=Sector address A20 to A9=Segment address
Bit5 X A14 X A5
Bit4 X A13 X A4
Bit3 A20 A12 X A3
Bit2 A19 A11 X A2
Bit1 A18 A10 A8 A1
Bit0 A17 A9 A7 A0
P/N: PM0819
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REV. 1.0, MAR. 04, 2003
MX25L1602
DEVICE OPERATION
1.Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2.When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS falling edge. In standby mode, SO pin of this LSI should be High-Z. 3.When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CSB rising edge.
COMMAND DESCRIPTION (1) Read Array
This command is sent with the 4-byte address (command included), and the byte address, followed by four dummy bytes sent to give the device time to stabilize. The device will then send out data starting at the byte address until CS goes high. The clock to clock out the data is supplied by the master SPI. The read operation is executed on a segment (512 bytes) basis. If the end of the segment is reached then the device will wrap around to the beginning of the segment.
(2) Read Status Register
When this command is sent, the device will continuously send out the status register contents starting at bit7. The clock to clock out the data is supplied by the master SPI. bit7
program/erase
bit6 NA
bit5 NA
completion Note1
bit4 erase error 1=error
bit3 program error 1=error
bit2 NA
bit1 NA
bit0 ready/busy 1=ready 0=busy
Bit 6,5,2,1 = Reserve for future use. Bit 4 = "1" -----> There is an error occurred in last erase operation. = "0" -----> There is no error occurred in last erase operation. Bit 3 = "1" -----> There is an error occurred in last program operation. = "0" -----> There is no error occurred in last program operation. Bit 0 ="1" -----> Device is in ready mode. ="0" -----> Device is in busy mode. Note 1:The initial value of Bit7 is "1". Bit7 will have "1" to "0" transit only after program/erase operation is completed. Bit7 will shift from "0" to "1" only after issued program/erase/Clear status register command.
(3) Clear Status Register This command only resets erase error bit (bit 4) and program error bit (bit 3) . These two bits are set by on-chip state machine during program/erase operation, and can only be reset by issuing a clear status register command or by powering down VCC . If status register indicates that error occurred in the last program/erase operation, any further program/erase operation will be prohibited until status register is cleared.
(4) Read ID This command is sent with an extra dummy byte( a 2-byte command). The device will clock out manufacturer code (C2H) and device code (01H) when this command is issued. The clock to clock out the data is supplied by the master SPI.
P/N: PM0819
5
REV. 1.0, MAR. 04, 2003
MX25L1602
(5) Sector/Chip Erase This command is sent with the sector address(A20~A13) when operating Sector Erase. The device will start the erase sequence after CS goes high without any further input. A sector should be erased in a typical of 300ms. The average current is less than 10mA. The chip erase operation does not require the sector address input but two extra dummy bytes are necessary. During this operation, customer can also access Read Status & Read ID operations.
(6) Page Program This command is sent with the page number(A20~A7), and byte address(A6~A0), followed by programming data. One to 128 bytes of data can be loaded into the buffer of the device until CS goes high. If the end of the page is reached, then the device will wrap around to the beginning of the page. The device will program the specified page with buffered data(Until CS goes high) without any further input. The typical page program time is 5ms. The average current is less than 10mA. During this operation, customer can also access Read Status & Read ID operations.
(7) Standby Mode When CS is high and there is no operation in progress, the device is put in standby mode. Typical standby current is less than 30uA.
POWER-ON STATE
After power-up, the device is placed in the standby state with following status: The status register is reset with following status : Bit 7 = "1" -----> Refer to page 5 for detail. Bit 6,5,2,1 = Reserve for future use. Bit 4 = "0" -----> Erase error flag is reset. Bit 3 = "0" -----> Program error flag is reset. Bit 0="1" -----> Device is in ready state.
P/N: PM0819
6
REV. 1.0, MAR. 04, 2003
MX25L1602
DATA SEQUENCE
Output data is serially sent out through SO pin, synchronized with the rising edge of SCLK, whereas input data is serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data is bit 7 (MSB) first, then bit 6, bit 5, ...., and bit 0.(LSB)
ADDRESS SEQUENCE
The address assignment is described as follows : BA: Byte address Bit sequence: AD1:First Address Bit sequence: AD2:Second Address Bit sequence: AD3:Thrid Address Bit sequence: X X A16 X A6 X A15 X A5 X A14 X A4 X A13 X A3 A20 A12 X A2 A19 A11 X A1 A18 A10 A8 A0 A17 A9 A7
P/N: PM0819
7
REV. 1.0, MAR. 04, 2003
MX25L1602
Auto Page Program Flow Chart Auto Chip Erase Flow Chart
START
START
F2H
F4H Set Chip Erase Command.
AD1
Dummy
Set Page Program
AD2
Command.
Dummy
AD3
83H
BA
Set Read Status Register Command. Dummy
Data are written (Until CS goes high)
Read Status Register
NO
83H Set Read Status Register Command. Dummy
Bit 7= 0?
YES
Read Status Register
Bit 4 = 0?
NO
YES
Bit7 = 0? NO
Chip Erase Completed
YES
Erase Error
NO
NO Bit3 = 0?
YES
Operation Done, Device stays at Read Status Register Mode until CS goes high.
To Continue Other Operation, Do Clear Status Register Command First
Pgae Program Completed
Program Error
YES
Program Another Page NO Operation Done, Device stays at Read Status Register Mode until CS goes high.
To Continue Other Operation, Do Clear Status Register Command First.
P/N: PM0819
8
REV. 1.0, MAR. 04, 2003
MX25L1602
Auto Sector Erase Flow Chart
START
F1H Set Sector Eraes AD1 Command.
AD2
83H Set Read Status Register Command. Dummy
Read Status Register
Bit7 = 0?
NO
YES
NO Bit4 = 0?
YES
Sector Erase Completed
Erase Error
YES
Erase Another Sector ?
To Continue Other Operation, Do Clear Status Register Command First.
NO Operation Done, Device stays at Read Status Register Mode until CS goes high.
P/N: PM0819
9
REV. 1.0, MAR. 04, 2003
MX25L1602
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential VALUE 0 to 70C C -55 to 125 C C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V
3.During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. 4.All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V. 2.Specifications contained within the following tables are subject to change. NOTICE: 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
0V -0.5V
4.6V 3.6V
20ns
CAPACITANCE TA = 25C, f = 1.0 MHz
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MIN. TYP MAX. 10 10 UNIT pF pF CONDITIONS VIN = 0V VOUT = 0V
P/N: PM0819
10
REV. 1.0, MAR. 04, 2003
MX25L1602
INPUT TEST WAVEFORMS AND MEASURESMENT LEVEL
3.0V 1.5V
AC Measurement Level
0V
Note:Input pulse rise and fall time are < 10ns
OUTPUT LOADING
DEVICE UNDER TEST
+3.3V
CL
DIODES=IN3064 OR EQUIVALENT
CL=50pF Including jig capacitance
P/N: PM0819
11
REV. 1.0, MAR. 04, 2003
MX25L1602
DC CHARACTERISTICS (Temperature = 0C to 70C, VCC = 3.0V ~ 3.6V)
SYMBOL PARAMETER IIL ILO ISB1 ISB2 ICC1 ICC2 ICC3 VIL VIH VOL VOH Input Load Current Output Leakage Current VCC Standby Current(CMOS) VCC Standby Current(TTL) VCC Read VCC Program Current VCC Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 1 -0.5 2.0 10 30 0.8 VCC+0.5 0.4 mA V V V V IOL = 500uA IOH = -100uA Erase in Progress 1 1 10 10 30 30 mA mA 1 3 mA 1 30 60 uA 1 10 uA NOTES MIN. 1 TYP MAX. 10 UNITS uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CS = VCC 0.2V VCC = VCC Max CS = VIH f=20MHz Program in Progress
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, T = 25C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation.
P/N: PM0819
12
REV. 1.0, MAR. 04, 2003
MX25L1602
AC CHARACTERISTICS (Temperature = 0C to 70C, VCC = 3.0V ~ 3.6V)
SYMBOL fSCLK tCYC tSKH tSKL tR tF tCSA tCSB tCSH tDS tDH tAA tDOH tDOZ tECY tPCY PARAMETER Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time CS Lead Clock Time CS Lag Clock Time CS High Time SI Setup Time SI Hold Time Access Time SO Hold Time SO Floating Time Erase Cycle Time Program Cycle Time 5 0 300 5 20 1600 15 50 50 100 5 25 30 50 25 25 6 6 Min. Typ. Max. 20 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms Conditions
NOTES: 1. Typical value is calculated by simulation.
SERIAL DATA INPUT/OUTPUT TIMING
tCSB tCSA tCSH
CS
tCYC tR tF
SCLK
tSKH tSKL
SI
tDS
BIT 7
tDH
BIT 6
BIT 0
SO
tAA
BIT 7
tDOH
BIT 0
tDOZ
P/N: PM0819
13
REV. 1.0, MAR. 04, 2003
MX25L1602
STANDBY TIMING WAVEFORM
CS SCLK SI SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Hi-Z 1st byte
When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS falling edge. In standby mode, SO pin of this LSI should be High-Z. While CS=VIH, current=standby current, while CS=VIL and commands are issuing, or commands are invalid, current=5mA(typ.) to 15mA(max.).
P/N: PM0819
14
REV. 1.0, MAR. 04, 2003
MX25L1602
READ ARRAY TIMING WAVEFORM
CS S C LK SI SO
B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 B it 1 B it 0 B it 7 B it 6 B it 5 B it 4
H i-Z 1st byte (52h ) 2n d b yte (AD1)
CS S C LK SI SO
9th b yte (Du mm y)
B it 1 B it 0
B it 7
B it 6
B it 5
B it 4
B it 3
B it 2
B it 1
B it 0
B it 7
B it 6
B it 5
1st data ou tp ut byte
2n d d ata o utpu t b yte
CS S C LK SI SO
B it 3 B it 2 B it 1 B it 0 B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 B it 1 B it 0
H i-Z
(N -1)th d ata o utpu t b yte
N th data ou tp ut byte
NOTES: 1. 1st Byte='52h' 2. 2nd Byte=Address 1(AD1), A17=BIT 0, A18=BIT1, A19=BIT2, A20=BIT3. 3. 3rd Byte=Address 2(AD2), A9=BIT0, A10=BIT1,......A16=BIT7 4. 4th Byte=Address 3(AD3), A7=BIT0, A8=BIT1 5. 5th Byte=Byte Address(BA), A0=BIT0, A1=BIT1,......A6=BIT6 6. 6th-9th Bytes for SI ==> Dummy Bytes (Don't care) 7. From Byte 10, SO Would Output Array Data
P/N: PM0819
15
REV. 1.0, MAR. 04, 2003
MX25L1602
READ STATUS REGISTER TIMING WAVEFORM
CS S C LK SI SO
B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 B it 1 B it 0 B it 7 B it 6 B it 5 B it 4
H i-Z 1st byte (83h ) 2n d b yte (Du mm y)
CS S C LK SI SO
2n d b yte (Du mm y)
B it 1 B it 0
B it 7
B it 6
B it 5
B it 4
B it 3
B it 2
B it 1
B it 0
B it 7
B it 6
B it 5
1st status o utpu t b yte
2n d statu s ou tp ut byte
CS S C LK SI SO
B it 3 B it 2 B it 1 B it 0 B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 B it 1 B it 0
H i-Z
(N-1)th statu s ou tp ut byte
N th status o utpu t b yte
NOTES: 1. BIT 7=0 ==> Program/Erase completed 2. BIT 4=1 ==>Erase Error 3. BIT 3=1 ==>Program Error 4. BIT 1,2,5,6 ==> Reserve for future use 5. Bit 0=1 ==> Device is in ready state
P/N: PM0819
16
REV. 1.0, MAR. 04, 2003
MX25L1602
CLEAR STATUS REGISTER TIMING WAVEFORM
CS SCLK SI SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Hi-Z 1st byte (89h)
NOTES: 1. 1st Byte='89h' ==> CLEAR STATUS REGISTER 2. SO at Hi-Z state
P/N: PM0819
17
REV. 1.0, MAR. 04, 2003
MX25L1602
READ ID TIMING WAVEFORM
CS SCLK SI SO
Bit7 Bit6 Bit0 Bit7 Bit6 Bit0
Hi-Z 1st byte (85h) 2nd byte (Dummy)
Bit7
Bit6
Bit0
Bit7
Bit6
1st ID byte (C2h)
2nd ID byte (01H)
CS SCLK SI SO
Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Hi-Z
(N-1) ID byte
N ID byte
NOTES: 1. 1st Byte:85h. 2. 2nd Byte:Dummy Byte. 3. 3rd Byte:Output Manufacture Code(C2h). 4. 4th Byte:Output Device Code(01H). 5. The 2 bytes ID output will be wrap around.
P/N: PM0819
18
REV. 1.0, MAR. 04, 2003
MX25L1602
AUTO PAGE PROGRAM TIMING WAVEFORM
CS SCLK SI SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4
Hi-Z 1st byte (F2h) 2nd byte (AD1)
CS SCLK SI SO
5th byte (BA) 1st write data byte 2nd write data byte
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
CS SCLK SI SO
(N-1)th write data byte Nth write data byte
Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Hi-Z
NOTES: 1. 1st Byte:F2h. 2. 2nd Byte:Address AD1. 3. 3rd Byte:Address AD2 4. 4th Byte:Address AD3 5. 5th Byte:Address BA. 6. 6th byte:1st write data byte. 7. When the last byte of the page will be written, the Byte Address will be wrap around to the first byte of the Page.
P/N: PM0819
19
REV. 1.0, MAR. 04, 2003
MX25L1602
AUTO SECTOR/CHIP ERASE TIMING WAVEFORM
CS SCLK SI SO
Bit 7 Bit 6 Bit 5 Bit 0 Bit 7 Bit 6 Bit 5 Bit 0 Bit 7 Bit 6 Bit 0
Hi-Z 1st byte - F1h for Sector Erase - F4h for Chip Erase 2nd byte - AD1 for Sector - Dummy for Chip 3rd byte - AD2 for Sector - Dummy for Chip
Hi-Z
NOTES: 1. 1st byte:F1h for Sector Erase, F4h for Chip Erase. 2. 2nd byte:Address AD1 for Sector Erase, Dummy byte for Chip erase. 3. 3rd byte:Address AD2 for Sector Erase, Dummy byte for Chip erase.
P/N: PM0819
20
REV. 1.0, MAR. 04, 2003
MX25L1602
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER Sector/Chip Erase Time Page Programming Time Chip Programming Time TYP.(1) 300 5 48 Max.(2) 1,600 15 240 UNIT ms ms s Excludes system level overhead(3) Comments
Note: 1.Typical program and erase time assumes the following conditions: 25C,3.3V, and checker board pattern. 2.Under worst conditions of 0C and 3.0V. 3.System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4.The maximum chip programming time is evaluated under the worst conditions of 0 VCC=3.0V, and 100K cycle C, with 90% confidence level.
ORDERING INFORMATION
PART NO. MX25L1602MC-50 ACCESS TIME 20MHz OPERATING CURRENT 10mA STANDBY CURRENT 30uA 28 pin SOP (330 mil) PACKAGE
P/N: PM0819
21
REV. 1.0, MAR. 04, 2003
MX25L1602
PACKAGE IMFORMATION
P/N: PM0819
22
REV. 1.0, MAR. 04, 2003
MX25L1602
REVISION HISTORY
Revision No. Description 1.0 1. Remove "Advanced Information" title Page P1 Date MAR/04/2003
P/N: PM0819
23
REV. 1.0, MAR. 04, 2003
MX25L1602
MACRONIX INTERNATIONAL CO., LTD.
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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